The advent of “stored-program” concept is considered to be a milestone in the history of computers. The basic idea of the stored-program concept is to store the instructions (of a program) in the computer memory along with data.
The idea is implicit in the design of Turing machine which was designed by Alan Turing in 1935. He described an abstract digital computing machine consisting of a limitless memory and a scanner that moved back and forth through the memory, symbol by symbol, reading what it finds and writing further symbols. The actions of the scanner are dictated by a program of instructions that is stored in the memory in the form of symbols. This is Turing's stored-program concept, and implicit in it is the possibility of the machine operating on and modifying its own program, but Turing did not recognized its importance in context of designing electronic computers.
The idea was applied in 1946 in the design of EDVAC (Electronic Discrete Variable Automatic Computer) by John von Neumann, John W. Mauchly and J. Presper Eckert. In June 1945, von Neumann independently published a paper entitled ‘First Draft of a report on EDVAC,’ in which he presented all of the basic elements of a stored-program computer. As a result, he got all the credit of the stored-program concept and the machines build using the concept are called “von Neumann machines” [2]. Generally, the term is now avoided in the professional circles as it is considered to be injustice to Mauchly and Eckert. It took a long time to build EDVAC. Before EDVAC was completed, a team coordinated by Maurice Wilkes at Cambridge University built the EDSAC computer. Thus EDSAC was the first stored-program computer actually built.
The motivation for introducing the stored-program concept came from the problems faced while working on ENIAC (Electronic Numerical Integration and Calculator),. ENIAC was the first general purpose computer (i.e. it could run different programs) but the new instructions had to be fed by changing the wiring of the computer [3]. This made the computer not only cumbersome and error prone but it also makes the use of computers, a specialized task. To overcome these problems, during the designing of the next computer, it was proposed that the instructions should be stored with data in the memory so that they can be changed easily. This also allows the program to branch to alternate instruction sequences based on previous calculations.
B. IMPLEMENTATION OF STORED-PROGRAM CONCEPT
Now I will show how to implement the stored-program concept in a basic computer (used in Morris Mano (1993)). The organization of the basic computer is defined by its internal registers, the timing and control structure, and the set of instructions that it uses.
B.1.THE BASIC COMPUTER HAS EIGHT REGISTERS, A MEMORY UNIT, AND A CONTROL UNIT.
B.1.a. REGISTERS AND MEMORY
The eight registers, there capacity and their function are shown in the following table.
Program counter (PC) is the register which stores the address of next instruction to be executed.The memory has 4096 words with 16 bits per word. To specify the address of each word a 12 bit number is needed (because, 212 = 4096).
Paths are required to transfer information from one register to another and between memory and registers; the wires will be excessive if connections are made between output of each register and inputs of all other registers. So, a common bus is used. The outputs and inputs of memory and all the registers are connected to the bus. Selection rules are defined to coordinate the use of bus.
B.1.b. COMPUTER INSTRUCTIONS
The basic computer has three instruction code formats as shown in the figure below. Each format has 16 bits.
The type of instruction is recognized by the control unit based on 4 bits in positions 12 through 15 of the instruction. If the opcode is not 111, then it is memory reference instruction. The bit in position 15 specifies the addressing mode (it is not required for present purpose) and the rest 12 bits specify the memory address. If the opcode is 111, then the control checks the bit 15, if bit 15 is 0 then it is a register reference instruction and it is 1 then it is an input-output instruction. Basic computer instructions are shown in the figure below.
B.1.c TIMING AND CONTROL
Master clock generator supplies pulses to all flip-flops and registers in the system. The pulses do not change the state of a register unless the register is enabled by a control signal. The control signals are generated in the control unit and provide control inputs for the common bus, for the processor registers and the micro-operations for the accumulator. The block diagram of the control unit is shown in the figure below.
An instruction is read and placed in Instruction register (IR). The IR is divided into three parts in the figure. The operation code in bits 12 to 14 is decoded using a 3X 8 decoder. Bit 15 is transferred to the flip-flop designated by I. Bits 0 to 11 are applied to the control logic gates. The output of sequence counter (SC) is decoded into 16 timing signals T0 to T15. SC can be incremented or cleared synchronously. SC is incremented with every positive clock transition unless its CLR input is active. For example, SC in incremented to provide timing signals T0, T1, T2, T3 and T4 in sequence. At time T4, SC is cleared to 0, if decoder D3 is active.
The last three waveforms in the figure show how SC is cleared when D3T4 =1. This is done by connecting the output of an AND gate whose inputs are D3 and T4 to the CLR of SC.
B.2 INSTRUCTION CYCLE
A program in the memory consists of a sequence of instructions. The program is executed by going through a cycle in turn is subdivided into a sequence of sub-cycles:
1. Fetch an instruction.
2. Decode the instruction.
3. Read from memory if instruction is indirect.
4. Execute the instruction.
B.2.A FETCH AND DECODE.
Initially, PC is loaded with the address of first instruction in the program and SC is cleared to 0, providing a timing signal T0. The micro-operations for fetch and decode can be specified as below:
T0: AR <-- PC T1: IR <-- M[AR], PC <-- PC +1 T2: D0,…,D7 <-- decode IR(12-14), AR <-- IR(0-11), I <-- IR(15) Since only AR is connected to the address inputs of the memory, it is necessary to transfer the address from PC to AR at T0. At T1, the instruction read from the memory is placed in the IR and PC is incremented to prepare it for the address of the next instruction. At T2, the operation code in IR is decoded, the indirect bit is transferred to flip-flop IR and the address part of instruction is transferred to AR.
Figure shows how first two register transfer statements are implemented in the bus system. It can be seen that at T0, the contents of PC are placed on the bus by making the selection inputs S2S1S0 equal to 010 and enabling the LD input of AR. Similarly the other instructions are carried out.
B.2.B DETERMINE THE FETCH AND DECODE.
The timing signal is active after T3. During the time T3, the control unit determines the type of instruction that was just read from the memory. The flow chart shows how the control determines the instruction type after the decoding.
The three instruction types are subdivided into four separate paths. The selected operation is activated with the clock transition associated with timing signal T3. This can be symbolized as follows:D’7IT3: AR <-- M[AR] D’7I’T3: Nothing. D7I’T3: Execute a register-reference instruction. D7IT3: Execute an input-output instruction. After the instruction is executed, SC is cleared to 0 and the control returns to the fetch phase with T0 =1. To execute an instruction various micro-operations need to be carried out. I will show how one memory reference instruction can be executed. Table lists the seven memory-reference instructions.
B.2.C EXECUTION OF THE INSTRUCTION.
I will describe the execution of the first instruction AND. This is an instruction that performs the AND logic operation on pairs of bits in AC and the memory word specified by the effective address. The data must be read from the memory and transferred to a register, so that it can be operated on with logic circuits. The micro-operations that execute this instruction are:
D0T4: DR ß M[AR]
D0T5: AC ß AC ^ DR, SCß o
In this way, other instructions can also be executed.
So it is obvious that instructions and data are stored on the same memory, what makes the difference is the way in which each is interpreted. This is done by placing the 16 bit instruction code in IR and placing the 16 bit data in DR. Now control checks the opcode from IR only and never from DR.
C. DRAWBACKS OF STORED-PROGRAM CONCEPT
The stored-program concept has found universal acceptability; most of the computers built today are based on the concept. But with the advances in the hardware, the concept is found to decrease the efficiency of the computer. Nowadays, the data transfer rate, between the CPU and memory is very low compared to the rate at which CPU works, thus CPU has to wait for a lot of time. This is called “von Neumann bottleneck”, a term coined by John Backus in his 1977 ACM Turing award lecture. According to Backus:
‘Surely there must be a less primitive way of making big changes in the store than by pushing vast numbers of words back and forth through the von Neumann bottleneck. Not only is this tube a literal bottleneck for the data traffic of a problem, but, more importantly, it is an intellectual bottleneck that has kept us tied to word-at-a-time thinking instead of encouraging us to think in terms of the larger conceptual units of the task at hand. Thus programming is basically planning and detailing the enormous traffic of words through the von Neumann bottleneck, and much of that traffic concerns not significant data itself, but where to find it.’ [4].
One of the solutions to “von Neumann bottleneck” is to introduce a fast memory ‘cache’ between CPU and conventional memory. Another candidate for solution is the “Harvard Architecture” (the term originated from the Harvard Mark I, a relay-based computer), in which the data and instructions are stored separately. It has an advantage over “von Neumann machines”, as it can access data and instructions in the same CPU cycle, which is not possible in “von Neumann machines”. Many modern chip designs incorporate the aspects of both Harvard architecture and von Neumann architecture.
D. REFERENCES:
1. http://www.maxmon.com/1946ad.htm
2. http://www.kingsford.org/khsWeb/computer/MicroComputers/History_of_ computers/04_the_stored_program_computer.htm
3. http://en.wikipedia.org/wiki/Stored_program
4. http://www.kingsford.org/khsWeb/computer/MicroComputers/ History_of_computers/03_first_generation_computers.htm
5. http://www.maxmon.com/1944ad.htm
6. http://plato.stanford.edu/entries/computing-history/#ENIAC
7. http://www.alanturing.net/turing_archive/pages/Reference%20Articles/ what_is_AI/What%20is%20AI03.html
8. http://webopedia.internet.com/TERM/V/Von_Neumann_machine.html
9. http://www.csc.liv.ac.uk/~ped/teachadmin/histsci/htmlform/lect4.html
10. http://courses.cs.deu.edu.tr/cse223/notes/assemblyprog/node11.html
11. http://www.ntu.edu.au/faculties/technology/schelectrical/staff/saeid/ teaching/ sen464/lectures/ch3/tsld013.html
12. http://concise.britannica.com/ebc/article?eu=404957
13. Mano, M. Morris, (1993),Computer System Architecture, Pearson Education: Singapore.
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